Expertise in Chip Design

1. Front-end
– RTL Coding (Verilog / VHDL)
– Functional and Gate Level
– Synthesis and Timing Analysis
– Re-Usable IP
– Soc Integration

2. Verification
– Custom Verification
– RTL Verification
– ATPG Verification
– PLL Verification
– Direct Test Verification
– BIST Verification
– BS Verification

3. Design for Test
– Internal Scan
– ATPG
– Boundary Scan
– BIST
– Expertise in Mentor, Logic and Synospys (DFT Tools)